The present invention is directed generally to memory devices, and more specifically to compensating for the effects of bit line coupling capacitance in two port memory devices.
Coupling capacitance between bit lines in memory devices can be sufficiently large to interfere with memory operations. Where the coupling capacitance is sufficiently large, data sense operations are delayed until enough bit line difference occurs for a read operation. Without any compensation for coupling capacitance, performance of the memory device is degraded due to the coupling capacitance. Prior systems typically implemented a twisted bit line configuration to reduce the coupling capacitance between bit lines in higher density bit line core designs. However, twisted bit line techniques are difficult to apply to multiport memory devices such as static random access memory (SRAM). For most memory devices, each bit line has a coupling effect on an adjacent bit line voltage swing. The coupling effect will cause the memory device to malfunction, or will reduce the performance of the device. Twisted bit line techniques have been applied to single port memories. Even when the bit lines are twisted as in single port memory, read and write data still have coupling capacitance issues, that is the coupling effect has merely been traded from being between a read line and a read line to being between a read line and a write line. For multiport memory, it is difficult to implement a twisted bit line scheme. Furthermore, implementing a twisted bit line approach to coupling capacitance requires extra area to accommodate the twists, and extra logic is still required in a twisted bit line scheme that also requires extra chip area. Therefore, a need exists to compensate for bit line coupling capacitance in multiport memory devices.
The present invention compensates for the effect of bit line coupling capacitance in multiport memory by providing compensation capacitance to reduce or eliminate the effect bit line coupling capacitance without requiring a twisted bit line scheme or extra logic circuits. In one embodiment, a compensation capacitance is added between read and write bar bit lines, and a compensation capacitance is added between write and read bar bit lines to compensate for the coupling capacitances between read and write bit lines and between write bar and read bar bit lines. The compensation capacitance may be added in a peripheral area at the perimeter of the core memory area of a semiconductor substrate, or may be incorporated within the core memory area itself.